1. Field of the Invention
The present invention relates to the field of data transfers between parallel processors, and more particularly, to an apparatus and method for routing and broadcasting data in a two dimensional mesh of processor nodes.
2. Art Background:
In recent years, parallel processing computer architectures have demonstrated substantial performance advantages over more traditional sequential computer architectures. In particular, as computational needs have grown, and the performance advantages offered by parallel processing have come to be recognized, highly parallel computer architectures have generated considerable interest. One such highly parallel computer architecture comprises a two dimensional mesh of processor nodes, each of these nodes coupled to an independent processor with computing power.
Within the two dimensional mesh, data must frequently be transferred from a first processor node to a second processor node. In addition, data must frequently be broadcast from a first processor node to many or all processor nodes. This can be a time consuming task if done entirely, or even partially, in software. Implementing the broadcast function in hardware significantly reduces the time needed to complete the broadcast task and therefore, improves the performance of the entire parallel processing system.
As will be described, the present invention implements data broadcasting in hardware, with minimal software intervention. Moreover, as will be described, the present invention implements data broadcasting a synchronously within a two dimensional mesh that is self-timed. As a result, the present invention provides for a low latency network with the additional routing feature of hardware data broadcasting.